FPGA Forth Interpreter CPU using an LFSR

This project details an FPGA CPU implemented in VHDL that utilizes a Linear Feedback Shift Register (LFSR) instead of a program counter. This approach, while traditionally space-saving, offers minimal benefits on FPGAs. The CPU, running a fully functional Forth interpreter, achieves 151.768MHz on a Spartan-6 FPGA. Remarkably compact, the core consumes only 27 slices. The project includes VHDL code, GHDL simulation instructions, and build instructions for Xilinx ISE 14.7. It showcases the potential of LFSRs for resource-constrained designs and presents a highly efficient Forth interpreter implementation.