Simulated SPI RAM on RP2040: A High-Performance Implementation

This project simulates an SPI RAM, similar to a 23LC512, on the RP2040 microcontroller. It supports READ, WRITE, and FAST READ commands, leveraging PIO and DMA for efficient data transfer. To meet stringent timing requirements, the simulated RAM utilizes Core1 and optimized PIO programs to minimize latency. While currently not supporting aborting operations before data transfer begins, this project offers an effective way to achieve high-performance SPI RAM on the RP2040.