SUS HDL: A More Intuitive Hardware Description Language
2025-07-07
SUS HDL is a new hardware description language (HDL) aimed at simplifying the hardware design process. Unlike Verilog or VHDL, SUS features latency counting for easier timing and pipelining, a compiler that tracks and displays design aspects in the editor, and powerful metaprogramming capabilities for generating LUTs. Its core philosophy is a clean syntax for direct netlist generation, compatible with traditional synthesis tools. While it requires synchronous hardware, its ease of use and powerful features make it a promising alternative.
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