Alder Lake SHLX Instruction Anomaly: A 3x Performance Mystery

Blogger Tavian Barnes uncovered a strange performance quirk in Intel's Alder Lake processors concerning the SHLX instruction. Under certain conditions, this instruction runs significantly slower—three times slower than expected. Benchmarking revealed that initializing the shift count register using a 64-bit immediate value causes the slowdown, while 32-bit instructions or other initialization methods do not. This discrepancy is puzzling since SHLX only uses the lower 6 bits of the shift count register. The root cause remains a mystery, but this finding highlights a potential optimization oversight in the Alder Lake microarchitecture.