VexRiscv: An FPGA-Friendly 32-bit RISC-V CPU Implementation

VexRiscv is an FPGA-friendly 32-bit RISC-V CPU implementation written in SpinalHDL. It features a configurable pipeline depth, various instruction set extensions (including M, A, F, D, C), and a highly extensible plugin system allowing for easy addition of custom instructions and features. The project offers a wide range of configurations, from simple RV32I to complex Linux-capable SoCs, and includes comprehensive documentation, tests, and examples for rapid deployment and debugging on FPGAs.