PCIe Endpoint on Xilinx 7-Series FPGAs: Open-Source Implementation

This project implements a PCIe endpoint on Xilinx 7-series FPGAs using the PCIE_2_1 hard block and GTP transceivers. It avoids proprietary Vivado IP cores and is compatible with openXC7. The design includes clock generation, GTP transceivers, and the PCIE_2_1 hard block, supporting PCIe Gen1 x1 and Gen2 x1. It's been tested on Alinx AC7100B SoM and Wavelet uSDR. Docker build and run scripts are provided, along with MSI interrupt and kernel driver support. This project is funded by NGI0 Entrust.