Running a 486 VM on the Sipeed Tang: An Amateur's Feat

The author successfully ported the MiSTer's ao486 PC core to the Sipeed Tang 138K FPGA, creating a project called 486Tang. This marks the first time ao486 has been successfully ported to a non-Altera FPGA. The port presented numerous challenges, including memory management (using SDRAM for main memory, DDR3 for the framebuffer), disk storage (direct SD card access), and a complex debugging process. To overcome the difficulties of hardware debugging, the author cleverly utilized Verilator for subsystem and whole-system simulation, using Bochs BIOS debug messages and custom tracing flags to pinpoint issues. Ultimately, through a series of performance optimizations such as reset tree and fan-out reduction, instruction fetch optimization, and TLB optimization, 486Tang achieved roughly 486SX-20 performance levels. This project showcases the author's impressive FPGA development skills and problem-solving abilities.