T1: A RISC-V Vector Processor Inspired by Cray X1
2025-02-06
T1 is a RISC-V vector processor implementation inspired by the Cray X1 vector machine. It features a lane-based microarchitecture with intensive chaining support and SRAM-based VRFs. Supporting standard Zve32f and Zve32x, T1 allows VLEN/DLEN scaling up to 64K, pushing the limits of the RISC-V Vector architecture. Key features include lanes, chaining, and a large LSU, while also serving as a general platform for MMIO DSAs. Designed with Chisel and accompanied by a T1Emulator, T1 integrates with any RISC-V scalar core. Users can configure T1 for various performance trade-offs, balancing throughput, area, and frequency, allowing for both high efficiency and high-performance designs.
Hardware
Vector Processor