Warping in Fan-out Wafer-Level Packaging: Modeling, Measurement, and Control
The end of Moore's Law has spurred advancements in advanced semiconductor packaging, such as fan-out wafer-level packaging (FOWLP). FOWLP enhances performance and efficiency by packaging chips at the wafer level and redistributing interconnects. However, warping during FOWLP manufacturing poses a significant challenge. This paper reviews methods for measuring (Moiré interferometry, digital fringe projection, digital image correlation), modeling (Stoney's equation, Timoshenko's theory, finite element method, AI/ML models, multi-scale approaches), and controlling warping. Warping is primarily determined by material properties (coefficient of thermal expansion, glass transition temperature, Young's modulus), process parameters (temperature profiles, mold cure rate, mold flow rate), and geometry (layer thickness, chip geometry, chip layout, redistribution layer). Future research directions include the need for more accurate material data, multi-scale models, and the development of digital twin technology for real-time warping control.