Beyond RISC-V: A Revolution in Distance-Based Instruction Set Architectures
CPU core instruction decoding and execution widths have significantly increased in recent years, but the cost of register renaming limits further scaling. This article introduces a distance-based instruction set architecture that eliminates register renaming by specifying operands based on the distance from the instruction's result, thus reducing hardware complexity and power consumption. Researchers have developed three distance-based instruction sets (STRAIGHT, Clockhands, and TURBULENCE) and successfully fabricated a chip based on the STRAIGHT instruction set. This innovation promises significant performance improvements for both CPUs and GPUs, especially for GPUs due to their flexible intermediate representation, making adoption easier.
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