Running RISC-V Binaries on AMD Zen CPUs via Microcode Modification
2025-04-09
A challenge calls for modifying the microcode of AMD Zen-series CPUs to enable direct execution of RISC-V binaries. Participants must complete microcode modifications, run RISC-V benchmark applications (e.g., Coremark, Dhrystone) on Zen CPUs, and compare performance against simulator-based emulation, demonstrating substantial improvement. Submissions require complete source code, configurations, and documentation to a specified GitHub repository.
Development
Microcode Modification