Skywater 130nm SerDes Design: High-Speed Communication Achieved
2025-06-18
This project details a high-speed Serializer/Deserializer (SerDes) circuit designed for high-speed communication. Implemented using Verilog HDL and synthesized with OpenLane on the Skywater OpenPDK 130nm process, the SerDes converts parallel data into a serial stream for transmission and back again at the receiver. The design includes a transmitter (using a chain of CMOS inverters as a driver), a receiver (employing a resistive feedback inverter and CMOS inverter for sensing and amplification), a D-flip-flop for data sampling, and an oversampling CDR for clock recovery. GDS, SPICE, and netlist files for all modules are provided.
Hardware
High-Speed Communication