TSMC Unveils Nanosheet Transistors: A New Era for Chips
TSMC showcased its next-generation N2 (2-nanometer) process at the IEEE International Electron Devices Meeting, marking its first foray into nanosheet transistors. Compared to its N3 process, N2 boasts up to a 15 percent speed increase, 30 percent better energy efficiency, and a 15 percent density boost. This new architecture offers greater flexibility, allowing for the creation of nanosheets with varying widths on the same chip, optimizing performance for different logic units, especially SRAM. Intel's research further validated the scalability of nanosheet architecture, demonstrating a high-performing 6-nanometer gate-length transistor, pointing the way towards continued advancement in chip technology and suggesting a potential extension of Moore's Law.
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