Impact of Extremely Low Temperatures on 5nm SRAM Array Size and Performance
New research explores the effects of extremely low temperatures (down to 10K) on the size and performance of 5nm FinFET SRAM arrays. Researchers found that at cryogenic temperatures, the maximum array size is limited by wordline parasitics, not leakage current, and performance is governed by both bitline and wordline parasitics. This has significant implications for future low-power, high-performance computing, offering valuable insights for optimizing SRAM arrays in extremely cold environments.
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